1. Field of the Invention
The invention relates generally to cache memory management, and specifically to providing ordered stores to a shared distributed cache memory system over an unordered network.
2. Background Information
It is well known to use fast cache memory between a processor and slow main memory in order to improve the average access time into slow main memory. Using cache memory can improve the execution performance of a processor. The cache memory was initially separate from the processor but later became an integral part of the processor as technology improved. With the cache memory being an integral part of the processor, access times to the cache memory could be further reduced.
Multiple levels of cache memory were introduced between the processor and the main memory. Typically, the speed of cache memory increased the closer the cache memory was to the processor but its sized decreased. Put differently, the size of cache memory typically increased and access time increased the further the cache memory was from the processor. However, multiple levels of cache memory complicated the cache management, particularly when instructions branched or jumped to another instruction or address into memory.
A memory controller or cache controller either internal or external to the processor was used to provide cache management of the cache memory between the main memory and the processor. Various cache memory management algorithms were introduced to maximize the use of the cache memory and reduce the number of misses into cache that required the processor to read data/instructions from the slow main memory or write data/instructions out to the slow main memory. Cache coherence protocols were introduced to maintain coherency of data stored in cache memories by tracking the state of data blocks that may be shared. Other cache memory management algorithms have been introduced.